The present invention relates to a semiconductor memory device having a redundancy relief circuit.
In general, a semiconductor memory device such as a static random access memory (SRAM) and a dynamic random access memory (DRAM) places a redundancy memory cell array in addition to a regular memory cell array on a chip in order to improve its yield. When it is determined that a defective memory cell exists in the regular memory cell array in the test process of the semiconductor memory device, the defective memory cell is replaced with the redundancy memory cell, thereby to complete the semiconductor memory device as a non-defective unit. That is, so-called redundancy relief is performed.
The technology of a prior art semiconductor memory device will be described below.
FIG. 14 is a configuration view of a semiconductor memory device (SRAM) of a first conventional example. The semiconductor memory device in FIG. 14 has memory cells 1, word-line drivers 2, a redundant word-line driver 3, a bit-line precharge control signal line driver 4, bit-line precharge circuits 5, word lines WL1 and WL2, a redundant word-line RWL, pairs of bit lines BL1, /BL1 and BL2, /BL2, and a bit-line precharge control signal line PCGL.
WLCG1 to WLCG 3 and PCG designate a word-line control signal and a bit-line precharge control signal, respectively, and “A” indicates a break in the word line.
The word-line drivers 2 are buffers connected to the respective word lines WL1 and WL2 and transmit the respective word-line control signals WLCG1 and WLCG2 to be inputted to memory cells 1 respectively through the respective word lines WL1 and WL2.
The redundant word-line driver 3 is a buffer connected to the redundant word-line RWL, and in the case where a defect exists in the word lines WL1 and WL2 and so on, the driver 3 transmits the word-line control signal WLCG3 to be inputted to memory cells 1 respectively through the redundant word-line RWL.
The bit-line precharge control signal line driver 4 is a buffer connected to the bit-line precharge control signal line PCGL, outputs the inputted bit-line precharge control signal PCG to the bit-line precharge control signal line PCGL and activates or deactivates the bit-line precharge circuits 5.
Each memory cell 1 is connected to a word line (including a redundant word line) and a pair of bit lines.
FIG. 15 is a circuit diagram showing the specific configuration of the memory cell 1. In FIG. 15, Q1 and Q2 are access transistors, Q3 and Q4 are drive transistors, Q5 and Q6 are load transistors, WL is a word line, BL and /BL are a pair of bit lines, and VDD is a power source terminal.
The gate terminals of the access transistors Q1 and Q2 are connected to the word line WL or the redundant word line RWL and drain terminals thereof are connected to the pair of bit lines BL and /BL, respectively.
The drive transistor Q3 and the load transistor Q5 form a first inverter and the drive transistor Q4 and the load transistor Q6 form a second inverter.
An output terminal of the first inverter is connected to an input terminal of the second inverter and an output terminal of the second inverter is connected to an input terminal of the first inverter so that a latch circuit is constituted. The latch circuit stores and holds data. When the word line WL or RWL (including the redundant word line) becomes H level, the memory cell 1 connected to the line outputs data stored therein to the pair of bit lines BL and /BL or receives input of a complementary signal (data) transmitted through the pair of bit lines BL and /BL.
FIG. 16 is a circuit diagram showing the specific configuration of the bit-line precharge circuit 5. In FIG. 16, Q7 and Q8 are precharge transistors, Q9 is an equalize transistor, BL and /BL are a pair of bit lines, PCGL is a bit-line precharge control signal line, and VDD is a power source terminal.
Each gate terminal of the precharge transistors Q7, Q8 and the equalize transistor Q9 is connected to the bit-line precharge control signal line. The drain terminals of the precharge transistors Q7 and Q8 are connected to the pair of bit lines BL and /BL, respectively and the source terminals are connected to the power source terminal VDD. The source terminal and drain terminal of the equalize transistor Q9 are connected to the pair of bit lines BL and /BL, respectively.
When the bit-line precharge control signal PCG is L level, the bit-line precharge circuits 5 become activated and precharge pairs of bit lines BL1, /BL and BL2, /BL2. When the bit-line precharge control signal PCG is H level, the bit-line precharge circuits 5 become deactivated and go into a high impedance state.
Operations of the semiconductor memory device thus constituted will be described below. Firstly, the case where no break A occurs in the word line will be explained.
When all of the word-line drivers 2 and the redundant word-line driver 3 output the word-line control signals WLCG1 to WLCG3 of L level, all memory cells 1 go into a high impedance state (the state in which data input/output is not performed). At that time, the bit-line precharge control signal PCG (output signal of the bit-line precharge control signal line driver 4) becomes L level and the bit-line precharge circuits 5 go into an activated state. All pairs of bit lines BL and /BL are precharged to H level (VDD level) by the bit-line precharge circuits 5.
Next, when the bit-line precharge control signal PCG becomes H level, the bit-line precharge circuits 5 go into a deactivated state (a high-impedance state).
When any one of all of the word-line drivers 2 and the redundant word-line driver 3 outputs H level, the memory cells 1 to which H level is inputted through the word line WL or RWL become activated (writing or reading of data is carried out). In the memory cell 1 which receives input of the word-line control signal WLCG of H level, gates of the access transistors Q1 and Q2 turns ON and writing or reading data to/from the latch circuits Q3 to Q6 is performed through the pair of bit lines BL and /BL connected to the access transistors Q1 and Q2, respectively.
When writing or reading data to/from the memory cells 1 is completed, the word-line control signal WLCG returns to L level from H level and the memory cells 1 go into a high impedance state. The bit-line precharge control signal PCG becomes L level again and the bit-line precharge circuits 5 are activated, so that the pairs of bit lines BL and /BL are precharged to H level. Subsequently, the above-mentioned processing is repeated.
Next, the case where a break A occurs in the word line will be described.
Suppose that a break occurs at the point indicated as A in FIG. 14. Even if the word-line driver 2 transmits the word-line control signal of H level through the word line WL1 with a break, it is impossible to properly write and read data to/from the memory cell connected to the word line WL1 on the right side from the break A.
In such a case, by performing redundancy relief mainly according to the below-mentioned method, a non-defective semiconductor memory device is completed. The word line WL1 with a break is made to L level (the input terminal of the word line driver 2 connected to the word line WL1 is connected to ground) and all memory cells 1 connected to the word line WL1 are made to be in a high impedance state. The word-line control signal WLCG inputted to the word line driver 2 connected to the word line WL1 is inputted to the redundant word-line driver 3. The redundant word-line driver 3 transmits the word-line control signal WLCG to the memory cells 1 through the redundant word line RWL, whereby that writing or reading data is performed in the memory cells 1 connected to the redundant word line RWL. By replacing the memory cells connected to the word line WL1 having a break with the memory cells connected to the redundant word line RWL, the semiconductor memory device can perform proper writing and reading of data.
However, the above-mentioned conventional configuration has problems as stated below.
In FIG. 14, even if an input terminal of the word-line driver 2 connected to the word line WL1 with a break is connected to ground, the word line WL1 remains in a floating state on the right side from the break point A at all times. In the case where the potential of the word line WL1 in a floating state equals the gate threshold of the access transistors Q1 and Q2 of the memory cell 1 or greater, all memory cells 1 connected to the word line on the right side from the break point A are always in an activated state (the state in which writing or reading of data is performed at all times).
Even if the memory cells connected to the word line WL1 with a break are replaced with memory cells connected to the redundant word line RWL, there is a possibility that the memory cells 1 connected to the word line in a floating state remain activated in the memory cell array. In the case where normal word lines other than the word line WL1 with a break (the word line WL2 or the redundant word line RWL in FIG. 14) become H level, data conflict between the memory cell 1 which is connected to the word line in a floating state and remains activated at all times and the memory cells 1 which are connected to the normal word lines and become activated may occur through the pair of bit lines (BL2 and /BL2 in FIG. 14), resulting in damaging data of memory cells 1 connected to the normal word lines.
In the period during which the bit-line precharge control signal PCG becomes L level and the pairs of bit lines are precharged to H level, the problem arises that pass-through current flows between the memory cell connected to the word line in a floating state and the bit-line precharge circuit. The above-mentioned problem arises when a break occurs in the word lines, and also when a break occurs in the redundant word line.
A semiconductor memory device described in Unexamined Patent Publication No. 11-213690 as a conventional example has means for dealing with the problem.
The semiconductor memory device described in Unexamined Patent Publication No. 11-213690 will be described referring to its figures and specification partly. FIG. 17 is a configuration view of a semiconductor memory device of a second conventional example.
FIG. 17 shows a memory cell array 30, a spare memory cell array 31, a row decoder 32, a spare row decoder 33, a column decoder 34, an input/output circuit 35, a pulldown circuit 36, static memory cells 20, spare static memory cells 21, NOR circuits 22, a pair of input/output lines 23, column selecting gates 24, a ground node 25, a break point 26 and parasitic capacitors between word lines 27.
The pulldown circuit 36 includes a plurality of N-type MOS transistors Q1 to Qm to pull down the potential of a plurality of word lines WL1 to WLm in the memory cell array 30 to ground potential. The plurality of N-type MOS transistors Q1 to Qm are provided corresponding to the plurality of word lines WL1 to WLm, respectively. Each of the N-type MOS transistors Q1 to Qm is connected between the terminal of the corresponding word line and the ground node 25 and turns ON in response to a spare enable signal NED of H level sent from a program circuit (not shown in FIG. 17).
The program circuit can program an address corresponding to a defective word line of the plurality of word lines WL1 to WLm. When a row address signal sent from an address buffer (not shown in FIG. 17) to the row decoder 32 indicates the programmed address, the program circuit generates the spare enable signal NED of H level. In response to the spare enable signal NED of H level, the spare row decoder 33 is activated and the row decoder 32 is deactivated.
Moreover, in response to the spare enable signal NED of H level, all of the N-type MOS transistors Q1 to Qm in the pulldown circuit 36 turn ON and all of the word lines WL1 to WLm in the memory cell array 30 are connected to the ground node 25.
In the case where the word line activated by the row address signal sent from the address buffer to the row decoder 32 is not a defective word line, the spare enable signal NED becomes L level. When the spare enable signal NED becomes L level, the static memory cells 20 connected to the word line of H level are brought into conduction (normal operation is carried out).
In FIG. 17, there exists the break 26 in the word line WL2 (corresponding to row address 2). The program circuit is set so that the spare enable signal NED becomes H level when the row address 2 is input. For example, when the spare word line SWL1 becomes H level at the row address 2, the defective word line WL2 is electrically replaced with the spare word line SWL1.
In the semiconductor memory device of the second conventional example, when the spare word line SWL1 as a substitute for the word line WL2 is activated to be H level, the terminal of the word line WL2 is connected to the ground node 25 through the N-type MOS transistor Q2. Accordingly, the potential of the part remote from the row decoder 32 of the world line WL2 (word line WL2 on the right side from the break point 26 in FIG. 17) is pulled down to the ground potential. Thus, when the spare word line SWL1 is activated, the word line WL2 never becomes activated, that is, no multi-selection occurs. As a result, correct data can be read out from the spare static memory cells 21 connected to the spare word line SWL1.
In the semiconductor memory device of the second conventional example, when the spare word line is activated, the potential of the word lines WL1 to WLm in the memory cell array 30 is pulled down by the N-type MOS transistors Q1 to Qm. This prevents the word line WLi (1≦i≦m) replaced with the spare word line SWLj (1≦j≦p) from going into a floating state and also prevents multi-selection of selecting the spare word line SWLj and the replaced word line WLi simultaneously from occurring.
With the above configuration, however, all of the pull-down transistors Q1 to Qm are in a deactivated state when a word line other than the redundant word line (for example, WL3) is selected. In the case where the potential of the word line WL2 with a break becomes a threshold of the memory cell or greater due to external effect (such as noise generated by coupling capacitor with other signal line), a similar problem in the above-mentioned conventional example can occur (multi-selection of selecting the word lines WL2 and WL3 simultaneously can occur). As wiring capacitor of the spare enable signal and gate capacitors of all pull-down transistors Q1 to Qm connected to the spare enable signal are charged or discharged according to selection or non-selection of the redundant word line, power consumption increases.
The present invention intends to solve the above-mentioned conventional problems and to provide a semiconductor memory device that ensures redundancy relief in the word line with a break at lower power consumption.
In the conventional semiconductor memory device, in the period during which the pairs of bit lines are precharged, the problem arises that pass-through current flows between the memory cells connected to the word line with a break and the bit-line precharge circuits. According to the present invention, in the period during which the pairs of bit lines are precharged, no pass-through current flows between the memory cells connected to the word line with a break and the bit-line precharge circuits and a semiconductor memory device that ensures redundancy relief in the word line with a break at lower power consumption is thus provided.